Method for manufacturing wiring substrates

ABSTRACT

A method is provided for manufacturing a wiring substrate having via conductors. The method includes the steps of providing a substrate having via holes which open at a surface of the substrate, and completely immersing the substrate, together with an electrode, into an electroplating solution in such a manner that the substrate extends vertically. Bubbles are generated in the solution at a position below the substrate such that the generated bubbles rise along the surface of the substrate, from a lower end to an upper end thereof, while striking the surface. Electric current is caused to flow between the electrode and the substrate to thereby form via conductors in the via holes.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for manufacturingwiring substrates and, more particularly, to a method for manufacturingwiring substrates including via conductors.

[0003] 2. Description of the Related Art

[0004] Wiring substrates including via conductors are well known. Thevia conductors are conventionally formed by the following steps. Asubstrate having via holes formed therein is first fabricated and thenis subjected to electroless plating so as to form an electroless platinglayer on the wall surface of each via hole. Subsequently, the substrateis immersed in an electroplating solution and subjected toelectroplating to thereby form an electroplated conductor on theelectroless plating layer of each via hole.

[0005] A disadvantage of this method is that, in some cases, a viaconductor having a predetermined desired shape is not formed in each viahole even after the electroplating operation. More specifically, in somevia holes, the electroplating fails to form a complete electroplatedconductor on the wall surface. In particular, in a case in which viaconductors to be formed are not cup-shaped via conductors, i.e., whereineach conductor assumes a shape conforming to that of the wall surface ofthe corresponding via hole, but rather are filled vias formed bycompletely filling the via holes with an electroplated conductor, theelectroplating operation frequently fails to form via conductors thatfill via holes to a sufficient, desired degree.

[0006] Possible reasons for the failure are as follows. Because the viaholes are indented or depressed relative to the surface of a substrate,when the substrate is immersed in a plating solution, air remains withinsome of the via holes, or air bubbles adhere to the wall surfaces ofsome via holes. In particular, in the case in which filled vias areformed, the shape of each via hole changes as an electroplated conductoris formed in the via hole, and, depending on the changed shape, airbubbles adhering to the wall surfaces of the via holes become difficultto remove. Since such air bubbles prevent plating of a sufficient supplyof the plating solution on the wall surfaces of the via holes, it isdifficult to provide uniform growth of the electroplated conductor. As aresult, the electroplated conductor is not fully formed on the wallsurfaces of some of the via holes.

SUMMARY OF THE INVENTION

[0007] The present invention is concerned with overcoming the problemsdiscussed above, and one object of the invention is to provide animproved method for manufacturing a wiring substrate including viaconductors which can be used to reliably form via conductors of desiredshapes irrespective of the locations thereof within the substrate.

[0008] In order to achieve this and other objects, according to thepresent invention, there is provided a method of manufacturing a wiringsubstrate including via conductors, the method comprising the steps of:providing a substrate having via holes opening at a surface of thesubstrate; immersing the substrate, together with an electrode,completely into an electroplating solution in such a manner that thesubstrate extends vertically; generating bubbles at a position below thesubstrate in such a manner that the bubbles rise along the surface ofthe substrate, from a lower end thereof to an upper end thereof, whilestriking the surface; and providing electric current flow between theelectrode and the substrate to thereby form via conductors in the viaholes.

[0009] In general, as indicated above, when a wiring substrate havingvia conductors is to be manufactured, a substrate having via holes isprepared and electroplating is then carried out in order to form viaconductors in the via holes. In the present invention, electroplating iseffected not only through mere immersion of the substrate into anelectroplating solution as is conventional. Rather, the substrate isimmersed in an electroplating solution so as to extend vertically, sothat the surfaces of the substrate are parallel to the vertical.Further, bubbling is performed in such a manner that bubbles generatedat a position below the substrate rise along the substrate, whileuniformly striking or otherwise contacting the entire substrate surfaceto be subjected to electroplating, from a lower end of the substrate toan upper end thereof, and thereafter rise further to a position abovethe substrate.

[0010] When electroplating is performed with bubbling, the bubblessuccessively strike the substrate surface as described above with theconsequence that any bubbles remaining within the via holes of theimmersed substrate are removed together with bubbles generated by meansof the bubbling operation. Moreover, even when air bubbles adhere to thevia holes of the substrate after immersion thereof, the air bubbles areremoved together with the generated bubbles. As result, theelectroplating solution is supplied to the entire wall surface of eachvia hole, and an electroplated conductor is formed which covers theentire wall surface of each via hole. Therefore, the present inventionenables reliable formation of via conductors of a desired shape.

[0011] It is also noted that, in accordance with the present invention,because the bubbles successively strike the entire substrate surface,from the lower end thereof to the upper end thereof, via conductors of adesired shape can be formed in the via holes irrespective of thepositions of the via holes on the substrate surface.

[0012] After the formation of via conductors, the formation of wiringlayers is carried out and other processes are performed by known methodsto thereby complete the wiring substrate.

[0013] According to a further aspect of the invention, the bubbles aregenerated as follows. A pipe having a large number of holes is disposedbelow the substrate and a gas, such as air, is fed to the pipe. As aresult, bubbles are generated, i.e., released through the holes in thepipe.

[0014] When via holes are to be formed on each of the opposite surfacesof the substrate, bubbling is performed in such a manner than bubblesstrike both of the opposite surfaces of the substrate. In this case, inaccordance with a preferred embodiment, two pipes capable of generatingbubbles are disposed with an appropriate separation therebetween suchthat bubbles generated from one pipe strike one surface of thesubstrate, whereas bubbles generated from the other pipe strike theother surface of the substrate.

[0015] In an important application, the manufacturing method of thepresent invention is applied to the manufacture of a wiring substrate inwhich via conductors assume the form of a filled via.

[0016] In the case in which the via conductors to be formed by theelectroplating process are not cup-shaped via conductors, i.e., areconductors assuming a shape conforming to that of the wall surface of acorresponding via hole, but rather are filled vias formed by filling thevia holes with an electroplated conductor, the electroplating frequentlyfails to produce via conductors of the desired shape, i.e., conductorsthat fill the via holes to a sufficient degree. Since the via holes aregradually filled with the electroplated conductor, the shapes of theholes (depressions) change accordingly, as the electroplating proceeds.Therefore, depending on the changed via-hole shape, air bubbles adheringto the wall surfaces of the via holes may be difficult to remove.

[0017] However, in accordance with the present invention, the substrateis oriented in the plating solution so as to extend vertically, andelectroplating is performed while bubbles are generated in such a mannerthat as the bubbles rise they strike or contact the complete substrate,i.e. both opposite facing surfaces of the substrate. As a consequence,even in the case in which the filled vias are formed in the via holes,electroplating can be properly performed because continuous adhesion ofthe bubbles to the via holes is prevented. As a result, the via holescan be completely filled with the electroplated conductor and filledvias of the desired shape are always formed.

[0018] Needless to say, when filled vias are formed in the via holes,i.e., when the via holes are to be completely filled, a plating solutionand plating conditions are employed which differ from those employed forformation of cup-shaped via conductors.

[0019] In one advantageous implementation, the substrate used in themanufacturing method of the present invention includes an underlyinglayer, and a plating resist layer which forms the substrate surface andhas openings for exposure of the underlying layer. The above-describedvia holes may then be formed in the underlying layer and exposed by theopenings in the plating resist layer.

[0020] In this case, the depth of each via hole, as measured from thesubstrate surface (the surface of the corresponding plating resistlayer), is greater than is the case wherein such a plating resist layeris not provided. Therefore, when the substrate is immersed in theelectroplating solution, air frequently remains within the via holes,with the resultant formation of air bubbles therein. Moreover, if theseair bubbles adhere to the via holes after immersion of the substrate,removal of such air bubbles becomes more difficult. As a result, viaconductors which are not of a desired shape may be formed in a greaternumber of cases than occur when such a plating resist layer is notprovided.

[0021] However, in accordance with the present invention, as describedabove, the substrate is disposed in the plating solution in a verticalorientation, and electroplating is performed while air bubbles aregenerated in such a manner that the bubbles strike the entire substratesurface(s) as they rise and, therefore, even in the case in which thevia holes have an increased depth by virtue of the presence of theplating resist layer, electroplating can be performed and air bubblesadhering to the via holes can be effectively removed. Therefore, viaconductors of a desired shape are universally formed.

[0022] It is also noted that electroplating is often performed for asubstrate carrying a plating resist layer, for example, in the case inwhich a wiring layer or other layer is formed on the surface of theunderlying layer by a semi-additive method. More specifically, byelectroless plating, an electroless plated layer is formed on thesurface of the underlying layer having via holes so as to cover theentire surface of the underlying layer and the wall surfaces of the viaholes. Subsequently, a plating resist layer is formed having an openingthat assumes a shape corresponding to that of a wiring layer. Thesubstrate in this state is the substrate which is used in the presentinvention, i.e., the substrate to be subjected to electroplating. Whenthe substrate undergoes electroplating, via conductors are formed, andelectroplating conductors are formed at portions corresponding to thewiring layer or a like layer. After completion of the electroplating,the plating resist layer is removed, and etching is performed so as toremove the thin electroless plating layer, so that a wiring layer, or alike layer of a desired pattern is formed.

[0023] Further features and advantages of the present invention will beset forth in, or apparent from, the detailed description of preferredembodiments thereof which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a partially broken away, cross sectional view of awiring substrate according to one embodiment of the present invention;

[0025]FIG. 2 is a view similar to that of FIG. 1, relating to a methodof manufacturing a wiring substrate according to the embodiment of FIG.1 and showing a substrate used in a copper electroplating step;

[0026]FIG. 3 is a cross sectional view relating to the method ofmanufacturing a wiring substrate according to the embodiment of FIG. 1and showing a copper electroplating step for forming filled vias; and

[0027]FIG. 4 is a view similar to that of FIG. 1, relating to the methodof manufacturing a wiring substrate according to the embodiment of FIG.1 and showing the state of the substrate after formation of filled viasby means of copper electroplating.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] One preferred embodiment of the present invention will next bedescribed in detail with reference to the drawings.

[0029] As indicated above, FIG. 1 is a partially broken away, crosssectional view of a wiring substrate, denoted 1, which is to bemanufactured by a method according to a preferred embodiment of thepresent invention. The wiring substrate 1 has the general shape of arectangular plate (400 mm×400 mm) and includes a main face 3 and areverse face 5. The wiring substrate 1 includes a plate-shaped coresubstrate (e.g., an insulating resin layer) 7 (having a typicalthickness of about 800 μm) located at the center of the substrate asreferenced relative to the thickness thereof. An insulating resin layer9 (having a typical thickness of about 35 μm) made of, for example,epoxy resin is formed on opposite sides of the insulating resin layer 7.Further, a solder resist layer (insulating resin layer) 11 (having atypical thickness of about 25 μm) made of, for example, epoxy resin isformed on each of the insulating resin layers 9.

[0030] A plurality of through-holes 13 (having a typical diameter ofabout 350 μm) is formed in the core substrate 7 at predeterminedpositions, as shown. A substantially cylindrical through-hole conductor15 (having a typical thickness of about 25 μm) is formed on the wallsurface of each through hole 13. A substantially columnar or cylindricalresin plug 17 fills the interior of the through-hole conductor 15. Inaddition, a plurality of via holes 19, each typically having an openingdiameter of about 85 μm, are formed in the insulating resin layers 9 atpredetermined positions and in such a manner that the via holes 19completely penetrate through the insulating resin layers 9. A filled via21 is formed in each of the via holes 19. Further, plural pad openings23 are formed in each of the solder resist layers 11 at predeterminedpositions, and in such a manner that the pad openings 23 completelypenetrate through the solder resist layers 11.

[0031] A first wiring layer 25 (having a typical thickness-of about 25μm) is formed between the core substrate 7 and each of the respectiveinsulating resin layers 9. Each first wiring layer 25 is connected tothe through hole conductor 15 and the corresponding filled vias 21. Inaddition, a second wiring layer 27 (having a typical thickness of about15 μm) is formed between each of the insulating resin layers 9 and thecorresponding solder resist layer 11. Each second wiring layer 27 isconnected to the corresponding filled via 21. Further, pads 27 p, whichare portions of the second wiring layers 27, are exposed within padopenings 23 of the solder resist layers 11. In order to preventoxidation of the pads 27 p, a nickel plating layer and a gold platinglayer (not shown) are formed, in this particular sequence, on each ofthe pads 27 p.

[0032] The wiring substrate 1 having the above-described structure, ismanufactured in a manner which will now be described.

[0033] First, as shown in FIG. 2, a double-sided copper-clad substrateis prepared as the core substrate 7, and a plurality of through-holes 13are formed in the core substrate 7 at predetermined positions.

[0034] Subsequently, the core substrate 7 is subjected to copperelectroless plating and then copper electroplating. Plating layers arethus formed on the opposite sides of the core substrate 7 in such amanner as to cover substantially the entire surface of the copper filmon each side, and the substantially cylindrical through-hole conductor15 (see FIG. 1 and FIG. 2) is formed on the wall surface of each of thethrough-holes 13.

[0035] Subsequently, the resin plug 17 is formed in each of thethrough-hole conductors 15. More specifically, by use of a mask (notshown) of a predetermined pattern having holes which correspond inposition and diameter to the positions and diameter of the through holeconductors 15, a resin paste is charged, through printing, into theinteriors of the through-hole conductors 15. Subsequently, the resinpaste is cured through the application of heat to thereby produce theresin plugs 17. The opposite ends of each resin plug 17 are polished soas to be flush with the corresponding surfaces of the core substrate 7.

[0036] After formation of the resin plugs 17, each copper layer,consisting of a copper film and a copper plating layer, is patterned soas to form the first wiring layers 25 on opposite sides of the coresubstrate 7. More specifically, a semi-hardened etching resist layer isformed on the copper layer, exposed to light through a mask (not shown)having a predetermined pattern corresponding to that of the first wiringlayer 25, and then subjected to development. Subsequently, the etchingresist layer is hardened through the application of heat, so as toproduce a hardened etching resist layer having a predetermined pattern.Subsequently, exposed portions of the copper layer, i.e., portions notcovered by the resist layer, are removed through etching. Aftercompletion of the etching operation, the etching resist layer isremoved.

[0037] In the next step, the insulating resin layers 9 having the viaholes 19 (having a typical opening diameter of about 85 μm) are formedon the first wiring layer 25 and the core substrate 7. Morespecifically, semi-hardened insulating resin layers are formed on thefirst wiring layer 25 and the core substrate 7, exposed to light througha mask (not shown) having a predetermined pattern corresponding to thatof the via holes 19, and then subjected to development. Subsequently,the insulating resin layers are hardened through application of heat,thereby forming the insulating resin layers 9 having the via holes 19 atpredetermined positions. It is noted that the via holes 19 may be formedby means of laser machining.

[0038] Next, an electroless copper plating operation is performed,whereby, as represented by the bold line in FIG. 2, an electrolesscopper plating layer 31 (having a typical thickness of about 0.7 μm) isformed on the surface of each of the first resin dielectric layers 9 andon the wall surfaces of the via holes 19.

[0039] Subsequently, a plating resist layer 33 of a predeterminedpattern having a plurality of openings 35 is formed on each of theelectroless copper plating layers 31. More specifically, a semi-hardenedplating resist layer is formed on each of the electroless copper platinglayers 31, exposed to light through a mask (not shown) having apredetermined pattern corresponding to the second wiring layer 27 andthe via holes 19, and then subjected to development. Subsequently,through hardening upon application of heat, the plating resist layer 33,having the openings 35 at predetermined positions, is formed. It isnoted that the openings 35 have various shapes corresponding to those ofthe second wiring layer 27 and the via holes 19.

[0040] As a result of the steps just described, a substrate 51 shown inFIG. 2 is obtained.

[0041] Next, in a copper electroplating step, the substrate 51 issubjected to copper electroplating. Before considering the copperelectroplating step, a plating apparatus 101 used in the electroplatingstep will be described with reference to FIG. 3. The plating apparatus101 is equipped with a non-illustrated moving unit for moving thesubstrate 51 while holding the same. The moving unit includes a rack(not shown) for holding the substrate 51, and a moving mechanism (notshown) for moving the rack in horizontal and vertical directions.

[0042] The plating apparatus 101 also includes a copper plating bath 103for forming copper electroplated conductors on the substrate 51. Thecopper plating bath 103 stores a copper electroplating solution 105 forforming the filled vias 21. Further, two pipes 107 are disposed in thevicinity of the bottom surface 103 t of the copper plating bath 103.Each of the pipes 107 typically has a length of about 800 mm andincludes a large number of holes formed therein for generating bubbles109. The pipes 107 are disposed parallel to each other, with a distanceH (typically of about 60 mm) therebetween, and extend parallel to thebottom surface 103 t of the copper plating bath 103. Accordingly, whenair is fed to the pipes 107, a large number of bubbles 109 are generatedfrom the holes in the pipes 107, and move upwardly to the surface of thecopper electroplating solution 105.

[0043] With this background, the copper electroplating step will bedescribed.

[0044] First, by means of the moving unit described above, the substrate51, placed on the rack of the moving unit, is moved horizontally to aposition above the copper plating bath 103.

[0045] Subsequently, the rack is moved downward in order to immerse thesubstrate 51 into the copper electroplating solution 105 stored in thecopper plating bath 103. At this time, the substrate 51 is oriented in avertical position or posture such that the opposite surfaces 53 of thesubstrate 51 face horizontally, as shown in FIG. 3. Further, anelectrode 110 made of copper is immersed in the copper electroplatingsolution 105 such that the electrode 110 extends vertically. Thesubstrate 51 (and, more specifically, the electroless copper platinglayers 31 of the substrate 51 shown in FIG. 2) and the electrode 110 areconnected to a power supply PS, and the power supply PS is turned on inorder to cause current to flow between the substrate 51 and theelectrode 110. After immersion over a predetermined period of time, acopper electroplating conductor is formed on each of the oppositesurfaces 53 of the substrate 51, as shown in FIG. 4. Thus, the filledvias 21 and the second wiring layers 27 are formed on the substratesurfaces 53.

[0046] In the copper electroplating step, copper electroplating iseffected not only through mere immersion of the substrate 51 into thecopper electroplating solution 105. Air is fed to the pipes 107 disposedbelow the substrate 51 to thereby generate the large number of bubbles109 (see FIG. 3). Specifically, in an exemplary embodiment, air is fedto the pipes 107 at a rate of 40 to 60 l/min, so that air flows out eachpipe 107 in the form of bubbles 109 at a rate of 20 to 30 l/min.

[0047] The bubbles 109 rise along the substrate surfaces 53, from theirlower end portions 53 d to upper end portions 53 u, while striking orhitting the surfaces 53, and rise further to a position above thesubstrate 51. In other words, when copper electroplating is performed,bubbles 109 are generated in such a manner that the bubbles 109 strikeor contact the substrate surfaces 53 in a uniform manner irrespective ofthe location thereon, and the bubbles 109 ultimately rise to a positionabove the substrate 51 without remaining at the upper end portions 53 u.

[0048] It is noted that the via holes 19 are formed on each of theopposite substrate surfaces 53. Therefore, the bubbling is performed insuch a manner that bubbles 109 strike both the opposite substratesurfaces 53. Since the two pipes 107 are disposed within the copperplating bath 103 with the space H formed therebetween, bubbles 109generated from one pipe 107B strike or hit one substrate surface 53B,whereas bubbles 109 generated from the other pipe 107C strike or hit theopposite substrate surface 53C. Since the length (about 800 mm) of thepipes 107 is set to be about two times the length (400 mm) of the sidesof the substrate 51, about one half (10 to 15 l/min) of the bubbles 109generated from the pipes 107 (20 to 30 l/min) come into contact witheach substrate surface 53.

[0049] When copper electroplating is performed with the associatedbubbling described above, any air bubbles remaining within the via holes19 of the immersed substrate 51 are removed together with the generatedbubbles 109. Moreover, even when air bubbles adhere to the via holes 19of the substrate 51 after immersion thereof, the air bubbles are removedtogether with the generated bubbles 109. As result, the copperelectroplating solution 105 is supplied to the entire wall surface ofeach via hole 19, and a copper electroplating conductor is formed whichcovers the entire wall surface of each via hole 19. Therefore, thefilled vias 21 are uniformly of a desired shape.

[0050] Moreover, since the bubbles 109 successively strike or come intocontact with the entire substrate surfaces 53, from their lower endportions 53 d to their upper end portions 53 u, the filled vias 21 of adesired shape can be formed in the via holes 19 irrespective of theirpositions on the substrate surfaces 53.

[0051] In the present embodiment, the vias to be formed through copperelectroplating are the filled vias 21 each formed of a copperelectroplated conductor that fills the corresponding via hole 19. Ingeneral, the vias are difficult to form in such a manner that the viaholes 19 are completely filled with the copper electroplated conductor.Since the via holes 19 are gradually filled with the copperelectroplated conductor, the shapes of the holes (depressions) changeaccordingly. Therefore, depending on the resultant via-hole shape, airbubbles adhering to the wall surfaces of the via holes 19 may bedifficult to remove.

[0052] However, in the present embodiment, as indicated above, thesubstrate 51 is oriented in the plating solution 105 so as to extendvertically, and the copper electroplating is performed while air bubbles109 are generated in such a manner that they rise while striking theentire substrate surfaces 53. Therefore, even in the case in which thefilled vias 21 are formed in the via holes 19, the copper electroplatingcan be properly performed, while continuous adhesion of the bubbles 109to the via holes 19 is prevented. As a result, the via holes 19 canalways be filled with the copper electroplated conductor as desired, andthus filled vias 21 of a desired shape are formed.

[0053] In the present embodiment, the substrate 51 to be subjected tocopper electroplating includes the insulating resin layers (underlyinglayers) 9 and the plating resist layers 33, which form the substratesurfaces 53 and have openings 35 for exposure of the insulating resinlayers 9. The via holes 19 in which the filled via 21 are to be formedare formed in the insulating resin layers 9 and exposed within theopenings 35 of the plating resist layers 33. Therefore, the depth ofeach via hole 19, as measured from the corresponding substrate surface53 (the surface of the corresponding plating resist layer 33), isgreater as compared with the case in which the plating resist layers 33are not provided. Therefore, when the substrate 51 is immersed in thecopper electroplating solution 105, air more frequently remains withinthe via holes 19, with the resultant formation of air bubbles therein.Further, if air bubbles adhere to the via holes 19 after immersion ofthe substrate 51, removal of such air bubbles is more difficult. As aresult, the filled via 21 of a desired shape may not be formed in alarger number of cases as compared with the case in which the platingresist layers 33 are not provided.

[0054] However, in the present embodiment, as described above, thesubstrate 51 is immersed in the plating solution 105 in a verticalorientation or posture, and copper electroplating is performed, whileair bubbles 109 are generated in such a manner that they rise whilestriking the entire substrate surfaces 53. Therefore, even in the casein which the via holes 19 have an increased depth by virtue of thepresence of the plating resist layers 33, the copper electroplating canbe properly performed, while continuous adhesion of the bubbles 109 tothe via holes 19 is prevented. As a result, the filled vias 21 arealways of the desired shape.

[0055] When a predetermined period of time has elapsed after completionof the copper electroplating (i.e., after formation of the filled vias21), by means of the moving mechanism described above, the rack ispulled upwardly from the copper plating bath 103 and is then movedhorizontally to a next stage. The copper electroplating stage is thuscompleted.

[0056] Next, the plating resist layers 33 are removed from the substrate51 in order to expose the electroless copper plating layer 31 which hasbeen previously covered by the plating resist layers 33.

[0057] Subsequently, a so-called quick etching is performed in order toremove the exposed electroless copper plating layer 31.

[0058] Next, the solder resist layers 11 having the pad openings 23 areformed on the insulating resin layers 9 and the second wiring layers 27.Specifically, a semi-hardened solder resist layer is formed on each ofthe insulating resin layers 9 and the corresponding second wiring layer27, is exposed to light through a mask having a predetermined patterncorresponding to the pad openings 23, and is then subjected todevelopment. Subsequently, through hardening upon application of heat,the solder resist layers 11 of a predetermined pattern are formed.

[0059] Subsequently, a nickel plating layer and a gold plating layer areformed, in this sequence, on the exposed pads 27 p not covered by thesolder resist layers 11.

[0060] Thus, the wiring substrate 1 shown in FIG. 1 is completed.

[0061] It will be understood by those skilled in this art that, whilethe present invention has been described with reference to a preferredembodiment, the present invention is not limited thereto, but may bemodified as appropriate without departing from the spirit or scope ofthe invention.

[0062] It is also noted that the above embodiment is described inreference to a method of manufacturing a multi-layer resin wiringsubstrate 1 in which a plurality of insulating resin layers 7, 9, and 11and a plurality of wiring layers 25 and 27 are stacked one upon another.However, it will be appreciated that the present invention can beapplied to other types of wiring substrates, including ceramic wiringsubstrates, so long as via conductors are formed in their via holes bymeans of electroplating. Further, the core substrate may be amulti-layer core substrate having wiring layers therein.

[0063] Further, in the above-described embodiment, the via conductors 21assume the form of a filled via. However, the via conductors 21 mayassume the form of a conformal via in which each via hole 19 is notfilled completely with a plating material.

[0064] In addition, in the above-described embodiment, the viaconductors (filled vias) 21 are formed through copper plating. However,the present invention can also be applied to cases where the viaconductors (filled vias) 21 are formed through plating of another,different metal.

What is claimed:
 1. A method of manufacturing a wiring substrateincluding via conductors, said method comprising the steps of: providinga substrate having via holes opening at a surface of the substrate;immersing the substrate, together with an electrode, completely into anelectroplating solution in such a manner that the substrate extendsvertically; generating bubbles at a position below the substrate suchthat the bubbles rise along the surface of the substrate, from a lowerend thereof to an upper end thereof, while striking the surface of thesubstrate; and producing electric current flow between the electrode andthe substrate to thereby form via conductors in the via holes.
 2. Amethod of manufacturing a wiring substrate according to claim 1, whereinthe via conductors are caused to assume the form of a filled via.
 3. Amethod of manufacturing a wiring substrate according to claim 1, whereinthe substrate includes an underlying layer and a plating resist layer,said plating resist layer forming the substrate surface and havingopenings therein for exposure of the underlying layer; and the via holesare formed in the underlying layer and exposed by the openings in theplating resist layer.
 4. A method of manufacturing a wiring substrateaccording to claim 2, wherein the substrate includes an underlying layerand a plating resist layer, said plating resist layer forming thesubstrate surface and having openings therein for exposure of theunderlying layer; and the via holes are formed in the underlying layerand exposed by the openings in the plating resist layer.